- Ph. D., University of Illinois at Urbana-Champaign, 1987
- VLSI timing analysis and simulation
- Transistor/circuit level power leakage reduction
- Software debugging and verification
- Distributed data sharing and collaboration
A current work that a doctoral student and I are working on is to develop techniques to reduce leakage power of circuits during idle times. Two specific techniques are developed: (1) Leakage power behavior is examined for reordering serially connected transistor blocks. Based on that, we can then determine a primary input vector to a circuit to reduce its leakage power during idle mode. (2) Effect of body bias is studied for nano-scale transistor. A hybrid technique (mixing reverse body bias and forward body bias) is developed to reduce power leakage during idle mode. Another current work that a doctoral student and I are working on is to develop a tool for software debugging and verification. Traditional IDE allows setting of break points, but provides minimum supports in reasoning and bug locating. The goal of this research work is to allow programmers to query various properties of programs and help locating the causes of property violations. Another current work that a doctoral student and I are working on is to design a transistor level circuit simulator, which gives an accuracy near that of SPICE, and can handles much larger circuits in much less run time. Other research work involves distributed data sharing and collaboration, design of platform and protocol for emergency response systems, etc.
- VLSI timing analysis
- VLSI computer-aided design
- Transistor level leakage power reduction
- Multimedia information systems
- Modeling and performance evaluation of computer/communication systems
- Object-oriented databases
- Computer networks
- Parallel/distributed processing
- Computer architecture
Don P. McGarry, C.Y. Roger Chen.; “IC.NET — Incident Command “Net”: A system using EDXL-DE for intelligent message routing,” 2010 IEEE International Conference on Technologies for Homeland Security (HST), pp. 197 – 203, Nov. 2010.
Jae Woong Chun and C. Y. Roger Chen, A Novel Leakage Power Reduction Technique for CMOS Circuit Design, IEEE International SoC Design Conference (ISOCC), Nov. 1010.
Veerapaneni Nagbhushan, C. Y. Roger Chen: Modeling and reduction of complex timing constraints in high performance digital circuits. IEEE International Conference on Computer Design (ICCD) 2009
Ting-Wei Chiang, C Y Roger Chen and Wei-Yu Chen , “A Technique for Selecting CMOS Transistor Orders,” IEEE International Conference on Computer Design (ICCD), Oct. 2007.
Ting-Wei Chiang, C Y Roger Chen and Wei-Yu Chen, “An Efficient Gate Delay Model for VLSI Design,” IEEE International Conference on Computer Design (ICCD), Oct. 2007.